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precision instrumentation amplifier ad8221 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its us e. specifications subject to change without notice. no license is granted by implication or otherwise unde r any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-910 6, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2011 analog devices, inc. all rights reserved. features easy to use available in space-saving msop gain set with 1 external resistor (gain range 1 to 1000) wide power supply range: 2.3 v to 18 v temperature range for specified performance: ?40c to +85c operational up to 125c 1 excellent ac specifications 80 db minimum cmrr to 10 khz (g = 1) 825 khz, C3 db bandwidth (g = 1) 2 v/s slew rate low noise 8 nv/hz, @ 1 khz, maximum input voltage noise 0.25 v p-p input noise (0.1 hz to 10 hz) high accuracy dc performance (ad8221br) 90 db minimum cmrr (g = 1) 25 v maximum input offset voltage 0.3 v/c maximum input offset drift 0.4 na maximum input bias current applications weigh scales industrial process controls bridge amplifiers precision data acquisition systems medical instrumentation strain gages transducer interfaces general description the ad8221 is a gain programmable, high performance instrumentation amplifier that delivers the industrys hi ghest cmrr over frequency in its class. the cmrr of instr umentation amplifiers on the market today falls off at 200 hz. in c ontrast, the ad8221 maintains a minimum cmrr of 80 db to 10 k hz for all grades at g = 1. high cmrr over frequency allows th e ad8221 to reject wideband interference and line harm onics, greatly simplifying filter requirements. possible applications include precision data acquisition, biomedical analysis, an d aerospace instrumentation. connection diagram 87 6 5 12 3 4 Cin r g r g +v s v out ref Cv s +in to p view ad8221 03149-001 figure 1. 40 50 60 70 80 90 cmrr (db) 100 110 120 frequency (hz) 100 10 1k 10k 100k 03149-002 ad8221 competi tor 1 competitor 2 figure 2. typical cmrr vs. frequency for g = 1 low voltage offset, low offset drift, low gain drift, hi gh gain accuracy, and high cmrr make this part an excellent cho ice in applications that demand the best dc performance po ssible, such as bridge signal conditioning. programmable gain affords the user design flexibility. a sing le resistor sets the gain from 1 to 1000. the ad8221 operat es on both single and dual supplies and is well suited for applicati ons where 10 v input voltages are encountered. the ad8221 is available in a low cost 8-lead soic and 8-le ad msop, both of which offer the industrys best performanc e. the msop requires half the board space of the soic, making it ideal for multichannel or space-constrained applications. performance is specified over the entire industrial tem perature range of ?40c to +85c for all grades. furthermore , the ad8221 is operational from ?40c to +125c 1 . 1 see typical performance characteristics for expected operation from 85c to 125c.
ad8221* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad62x, ad822x, ad842x series inamp evaluation board documentation application notes ? an-1401: instrumentation amplifier common-mode range: the diamond plot ? an-282: fundamentals of sampled data systems ? an-671: reducing rfi rectification errors in in-amp circuits ? an-683: strain gage measurement using an ac excitation data sheet ? ad8221-dscc: military data sheet ? ad8221-ep: enhanced product data sheet ? ad8221: precision instrumentation amplifier data sheet technical books ? a designer's guide to instrumentation amplifiers, 3rd edition, 2006 user guides ? ug-261: evaluation boards for the ad62x, ad822x and ad842x series tools and simulations ? ad8221 spice macro-model reference designs ? cn0114 reference materials technical articles ? eye movement controls gaming console ? high-performance adder uses instrumentation amplifiers ? input filter prevents instrumentation-amp rf-rectification errors ? ms-2160: mitigation strategies for ecg design challenges ? ms-2178: discussion between carefusion and analog devices: optimizing performance and lowering power in an eeg amplifer ? the ad8221 - setting a new industry standard for instrumentation amplifiers design resources ? ad8221 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad8221 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ad8221 rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 connection diagram ....................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 8 thermal characteristics .............................................................. 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 17 gain selection ............................................................................. 18 layout .......................................................................................... 18 reference terminal .................................................................... 19 power supply regulation and bypassing ................................ 19 input bias current return path ............................................... 19 input protection ......................................................................... 19 rf interference ........................................................................... 20 precision strain gage ................................................................. 20 conditioning 10 v signals for a +5 v differential input adc ............................................................................................. 20 ac-coupled instrumentation amplifier ................................ 21 die information .............................................................................. 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 revision history 3/11rev. b to rev. c added pin configuration and function descriptions sec tion .. 9 added die information section ................................................... 22 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 24 9/07rev. a to rev. b changes to features .......................................................................... 1 changes to table 1 layout ............................................................... 3 changes to table 2 layout ............................................................... 5 changes to figure 15 ...................................................................... 11 changes to figures 32 .................................................................... 13 changes to figure 33, figure 34, and figure 35 ......................... 14 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 22 11/03rev. 0 to rev. a changes to features .......................................................................... 1 changes to specifications section .................................................. 4 changes to theory of operation section .................................... 13 changes to gain selection section............................................... 14 10/03revision 0: initial version
ad8221 rev. c | page 3 of 24 specifications v s = 15 v, v ref = 0 v, t a = 25c, g = 1, r l = 2 k, unless otherwise noted. table 1. ar grade br grade parameter conditions min typ max min typ max unit common-mode rejection ratio cmrr dc to 60 hz with 1 k source imbalance v cm = ?10 v to +10 v g = 1 80 90 db g = 10 100 110 db g = 100 120 130 db g = 1000 130 140 db cmrr at 10 khz v cm = ?10 v to +10 v g = 1 80 80 db g = 10 90 100 db g = 100 100 110 db g = 1000 100 110 db noise rti noise = e ni 2 + (e no /g) 2 voltage noise, 1 khz input voltage noise, e ni v in+ , v in? , v ref = 0 8 8 nv/hz output voltage noise, e no 75 75 nv/hz rti f = 0.1 hz to 10 hz g = 1 2 2 v p-p g = 10 0.5 0.5 v p-p g = 100 to 1000 0.25 0.25 v p-p current noise f = 1 khz 40 40 fa/hz f = 0.1 hz to 10 hz 6 6 pa p-p voltage offset 1 input offset, v osi v s = 5 v to 15 v 60 25 v over temperature t = ?40c to +85c 86 45 v average tc 0.4 0.3 v/c output offset, v oso v s = 5 v to 15 v 300 200 v over temperature t = ?40c to +85c 0.66 0.45 m v average tc 6 5 v/c offset rti vs. supply (psr) v s = 2.3 v to 18 v g = 1 90 110 94 110 db g = 10 110 120 114 130 db g = 100 124 130 130 140 db g = 1000 130 140 140 150 db input current input bias current 0.5 1.5 0.2 0.4 na over temperature t = ?40c to +85c 2.0 1 na average tc 1 1 pa/c input offset current 0.2 0.6 0.1 0.4 na over temperature t = ?40c to +85c 0.8 0.6 na average tc 1 1 pa/c reference input r in 20 20 k i in v in+ , v in? , v ref = 0 50 60 50 60 a voltage range Cv s +v s Cv s +v s v gain to output 1 0.0001 1 0.0001 v/v
ad8221 rev. c | page 4 of 24 ar grade br grade parameter conditions min typ max min typ max unit power supply operating range v s = 2.3 v to 18 v 2.3 18 2.3 18 v quiescent current 0.9 1 0.9 1 ma over temperature t = ?40c to +85c 1 1.2 1 1.2 m a dynamic response small signal ?3 db bandwidth g = 1 825 825 khz g = 10 562 562 khz g = 100 100 100 khz g = 1000 14.7 14.7 khz settling time 0.01% 10 v step g = 1 to 100 10 10 s g = 1000 80 80 s settling time 0.001% 10 v step g = 1 to 100 13 13 s g = 1000 110 110 s slew rate g = 1 1.5 2 1.5 2 v/s g = 5 to 100 2 2.5 2 2.5 v/s gain g = 1 + (49.4 k/r g ) gain range 1 1000 1 1000 v/v gain error v out 10 v g = 1 0.03 0.02 % g = 10 0.3 0.15 % g = 100 0.3 0.15 % g = 1000 0.3 0.15 % gain nonlinearity v out = ?10 v to +10 v g = 1 to 10 r l = 10 k 3 10 3 10 ppm g = 100 r l = 10 k 5 15 5 15 ppm g = 1000 r l = 10 k 10 40 10 40 ppm g = 1 to 100 r l = 2 k 10 95 10 95 ppm gain vs. temperature g = 1 3 10 2 5 ppm/c g > 1 2 C50 C50 ppm/c input input impedance differential 100||2 100||2 g||pf common mode 100||2 100||2 g||pf input operating voltage range 3 v s = 2.3 v to 5 v Cv s + 1.9 +v s ? 1.1 Cv s + 1.9 +v s ? 1.1 v over temperature t = ?40c to +85c Cv s + 2.0 +v s ? 1.2 Cv s + 2.0 +v s ? 1.2 v input operating voltage range v s = 5 v to 18 v Cv s + 1.9 +v s ? 1.2 Cv s + 1.9 +v s ? 1.2 v over temperature t =?40c to +85c Cv s + 2.0 +v s ? 1.2 Cv s + 2.0 +v s ? 1.2 v output r l = 10 k output swing v s = 2.3 v to 5 v Cv s + 1.1 +v s ? 1.2 Cv s + 1.1 +v s ? 1.2 v over temperature t = ?40c to +85c Cv s + 1.4 +vs ? 1.3 Cv s + 1.4 +v s ? 1.3 v output swing v s = 5 v to 18 v Cv s + 1.2 +v s ? 1.4 Cv s + 1.2 +v s ? 1.4 v over temperature t = C40c to +85c Cv s + 1.6 +v s ? 1.5 Cv s + 1.6 +v s ? 1.5 v short-circuit current 18 18 ma
ad8221 rev. c | page 5 of 24 ar grade br grade parameter conditions min typ max min typ max unit temperature range specified performance C40 +85 C40 +85 c operating range 4 C40 +125 C40 +125 c 1 total rti v os = (v osi ) + (v oso /g). 2 does not include the effects of external resistor r g . 3 one input grounded. g = 1. 4 see typical performance characteristics for expected operation between 85c to 125c. table 2. parameter conditions arm grade unit min typ max common-mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbalance v cm = ?10 v to +10 v g = 1 80 db g = 10 100 db g = 100 120 db g = 1000 130 db cmrr at 10 khz v cm = C10 v to +10 v g = 1 80 db g = 10 90 db g = 100 100 db g = 1000 100 db noise rti noise = e ni 2 + (e no /g) 2 voltage noise, 1 khz input voltage noise, e ni v in+ , v in? , v ref = 0 8 nv/hz output voltage noise, e no 75 nv/hz rti f = 0.1 hz to 10 hz g = 1 2 v p-p g = 10 0.5 v p-p g = 100 to 1000 0.25 v p-p current noise f = 1 khz 40 fa/hz f = 0.1 hz to 10 hz 6 pa p-p voltage offset 1 input offset, v osi v s = 5 v to 15 v 70 v over temperature t = ?40c to +85c 135 v average tc 0.9 v/c output offset, v oso v s = 5 v to 15 v 600 v over temperature t = ?40c to +85c 1.00 mv average tc 9 v/c offset rti vs. supply (psr) v s = 2.3 v to 18 v g = 1 90 100 db g = 10 100 120 db g = 100 120 140 db g = 1000 120 140 db input current input bias current 0.5 2 na over temperature t = ?40c to +85c 3 na average tc 3 pa/c input offset current 0.3 1 na over temperature t = ?40c to +85c 1.5 na average tc 3 pa/c
ad8221 rev. c | page 6 of 24 parameter conditions arm grade unit min typ max reference input r in 20 k i in v in+ , v in? , v ref = 0 50 60 a voltage range ?v s +v s v gain to output 1 0.0001 v/v power supply operating range v s = 2.3 v to 18 v 2.3 18 v quiescent current 0.9 1 ma over temperature t = ?40c to +85c 1 1.2 ma dynamic response small signal C3 db bandwidth g = 1 825 khz g = 10 562 khz g = 100 100 khz g = 1000 14.7 khz settling time 0.01% 10 v step g = 1 to 100 10 s g = 1000 80 s settling time 0.001% 10 v step g = 1 to 100 13 s g = 1000 110 s slew rate g = 1 1.5 2 v/s g = 5 to 100 2 2.5 v/s gain g = 1 + (49.4 k/r g ) gain range 1 1000 v/v gain error v out 10 v g = 1 0.1 % g = 10 0.3 % g = 100 0.3 % g = 1000 0.3 % gain nonlinearity v out = ?10 v to +10 v g = 1 to 10 r l = 10 k 5 15 ppm g = 100 r l = 10 k 7 20 ppm g = 1000 r l = 10 k 10 50 ppm g = 1 to 100 r l = 2 k 15 100 ppm gain vs. temperature g = 1 3 10 ppm/c g > 1 2 C50 ppm/c input input impedance differential 100||2 g/pf common mode 100||2 g/pf input operating voltage range 3 v s = 2.3 v to 5 v Cv s + 1.9 +v s ? 1.1 v over temperature t = ?40c to +85c Cv s + 2.0 +v s ? 1.2 v input operating voltage range v s = 5 v to 18 v Cv s + 1.9 +v s ? 1.2 v over temperature t = ?40c to +85c Cv s + 2.0 +v s ? 1.2 v output r l = 10 k output swing v s = 2.3 v to 5 v Cv s + 1.1 +v s ? 1.2 v over temperature t = ?40c to +85c Cv s + 1.4 +v s ? 1.3 v output swing v s = 5 v to 18 v Cv s + 1.2 +v s ? 1.4 v over temperature t = ?40c to +85c Cv s + 1.6 +v s ? 1.5 v short-circuit current 18 ma
ad8221 rev. c | page 7 of 24 parameter conditions arm grade unit min typ max temperature range specified performance ?40 +85 c operating range 4 ?40 +125 c 1 total rti v os = (v osi ) + (v oso /g). 2 does not include the effects of external resistor r g . 3 one input grounded. g = 1. 4 see typical performance characteristics for expected operation between 85c to 125c.
ad8221 rev. c | page 8 of 24 absolute maximum ratings table 3. parameter rating supply voltage 18 v internal power dissipation 200 mw output short-circuit current indefinite input voltage (common-mode) v s differential input voltage v s storage temperature range ?65c to +150c operating temperature range 1 ?40c to +125c 1 temperature range for specified performance is C40 c to +85c. see typical performance characteristics for expected operation f rom 85c to 125c. stresses above those listed under absolute maximum rati ngs may cause permanent damage to the device. this is a str ess rating only; functional operation of the device at the se or any other conditions above those indicated in the operat ional section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may aff ect device reliability. thermal characteristics specification for a device in free air. table 4. package ja unit 8-lead soic, 4-layer jedec board 121 c/w 8-lead msop, 4-layer jedec board 135 c/w esd caution
ad8221 rev. c | page 9 of 24 pin configuration and function descriptions top view (not to scale) Cin 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 Cv s 5 ad8221 03149-103 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 ?in negative input terminal. 2 r g gain setting terminal. place resistor across the r g pins to set the gain. g = 1 + (49.4 k/r g ). 3 r g gain setting terminal. place resistor across the r g pins to set the gain. g = 1 + (49.4 k/r g ). 4 +in positive input terminal. 5 ?v s negative power supply terminal. 6 ref reference voltage terminal. drive this termin al with a low impedance voltage source to level-shif t the output. 7 v out output terminal. 8 +v s positive power supply terminal.
ad8221 rev. c | page 10 of 24 typical performance characteristics t = 25c, v s = 15 v, r l = 10 k?, unless otherwise noted. 0 200 400 600 800 1000 units 1200 1400 1600 0 C50 C100 C150 50 100 150 cmr (v/v) 03149-003 figure 4. typical distribution for cmr (g = 1) 0 300 600 900 1200 1500 units 1800 2100 2400 0 C20 C40 C60 20 40 60 input offset voltage (v) 03149-004 figure 5. typical distribution of input offset voltage 0 500 1000 1500 2000 2500 3000 units 0 C0.5 C1.0 C1.5 0.5 1.0 1.5 input bias current (na) 03149-005 figure 6. typical distribution of input bias current 0 500 1000 1500 2000 2500 3000 3500 units 0 C0.3 C0.6 C0.9 0.3 0.6 0.9 input offset current (na) 03149-006 figure 7. typical distribution of input offset current C15 C10 C5 0 5 10 15 input common-mode voltage (v) C5 0 C15 C10 5 10 15 output voltage (v) 03149-007 v s = 5v v s = 15v figure 8. input common-mode range vs. output voltage, g = 1 C15 C10 C5 0 5 10 15 input common-mode voltage (v) C5 0 C15 C10 5 10 15 output vo ltage (v) 03149-008 v s = 5v v s = 15v figure 9. input common-mode range vs. output voltage, g = 100
ad8221 rev. c | page 11 of 24 0.40 0.45 0.50 0.55 0.60 0.65 input bias current (na) 0.70 0.75 0.80 C5 0 C15 C10 5 10 15 common-mode voltage (v) 03149-009 v s = 5v v s = 15v figure 10. i bias vs. cmv 0 0.25 0.50 0.75 1.00 1.25 change in input offset voltage (v) 1.50 1.75 2.00 0.1 0.01 1 10 warm-up time (min) 03149-010 figure 11. change in input offset voltage vs. warm-up time C5 C4 C3 C2 C1 0 1 2 3 4 5 input current (na) C40 C20 0 20 40 60 80 100 120 140 temperature (c) 03149-011 input bias current vs = 15v input offset current figure 12. input bias current and offset current vs. temperatur e 20 40 60 80 100 120 positive psrr (db) 140 160 180 0.1 1 10 100 1k 10k 100k 1m frequency (hz) 03149-012 gain = 1 gain = 10 gain = 100 gain = 1000 gain = 1000 figure 13. positive psrr vs. frequency, rti (g = 1 to 1000) 20 40 60 80 100 120 negative psrr (db) 140 160 180 0.1 1 10 100 1k 10k 100k 1m frequency (hz) 03149-013 gain = 1 gain = 10 gain = 100 gain = 1000 figure 14. negative psrr vs. frequency, rti (g = 1 to 1000) total drift 25c C 85c rti (v) 10 100 1k 10k 100k 1k 10k 10 100 100k 1m 10m source resistance ( ? 03149-014 best available fet input in-amp gain = 1 best available fet input in-amp gain = 1000 ad8221 gain = 1 ad8221 gain = 1000 figure 15. total drift vs. source resistance
ad8221 rev. c | page 12 of 24 C30 C20 C10 0 10 20 30 40 50 60 70 100 1k 10k 100k 1m 10m frequency (hz) gain (db) 03149-015 gain = 1000 gain = 100 gain = 10 gain = 1 figure 16. gain vs. frequency 40 60 80 100 cmrr (db) 120 140 160 0.1 1 10 100 1k 10k 100k 1m frequency (hz) 03149-016 gain = 1000 gain = 100 gain = 10 gain = 1 figure 17. cmrr vs. frequency, rti 40 60 80 100 cmrr (db) 120 140 160 0.1 1 10 100 1k 10k 100k 1m frequency (hz) 03149-017 gain = 1000 gain = 100 gain = 10 gain = 1 figure 18. cmrr vs. frequency, rti, 1 k source imbalance C100 C80 C60 C40 C20 0 20 40 60 80 100 cmr (v/v) C40 C20 0 20 40 60 80 100 120 140 temperature (c) 03149-018 figure 19. cmr vs. temperature Cv s +0 +0.4 +0.8 +1.2 +1.6 +2.0 +2.4 C1.6 C2.0 C2.4 C1.2 C0.8 C0.4 +v s C0 input voltage limit (v) referred to supply voltages supply voltage (v) 5 0 10 15 20 03149-019 figure 20. input voltage limit vs. supply voltage, g = 1 Cv s +0 +0.4 +0.8 +1.2 +1.6 +2.0 C1.6 C2.0 C1.2 C0.8 C0.4 +v s C 0 output voltage swing (v) referred to supply voltages supp ly voltage (v) 5 0 10 15 20 03149-020 r l = 10k ? r l = 2k ? r l = 10k ? r l = 2k ? figure 21. output voltage swing vs. supply voltage, g = 1
ad8221 rev. c | page 13 of 24 output voltage swing (v p-p) 0 20 10 30 load resistance ( ? 10 1 100 1k 10k 03149-021 v s = 15v figure 22. output voltage swing vs. load resistance Cv s +0 +1 +2 +3 C3 C2 C1 +v s C0 output voltage swing (v) referred to supply voltages 0 1 2 3 4 5 6 7 8 9 10 11 12 output current (ma) 03149-022 sourcing sinking figure 23. output voltage swing vs. output current, g = 1 C10 C8 C6 C4 C2 0 2 4 6 8 10 v s = 15v 03149-023 error (1ppm/div) output voltage (v) figure 24. gain nonlinearity, g = 1, r l = 10 k v s = 15v 03149-024 C10 C8 C6 C4 C2 0 2 4 6 8 10 error (10ppm/div) output voltage (v) figure 25. gain nonlinearity, g = 100, r l = 10 k v s = 15v 03149-025 C10 C8 C6 C4 C2 0 2 4 6 8 10 error (100ppm/div) output voltage (v) figure 26. gain nonlinearity, g = 1000, r l = 10 k voltage noise rti (nv/ hz) 1 100 10 1k 1 10 100 1k 10k 100k frequency (hz) 03149-026 gain = 1 gain = 1000 bw limit gain = 10 gain = 100 gain = 1000 figure 27. voltage noise spectral density vs. frequency (g = 1 to 1000)
ad8221 rev. c | page 14 of 24 1s/div 2v/div 03149-027 figure 28. 0.1 hz to 10 hz rti voltage noise (g = 1) 1s/div 0.1v/div 03149-028 figure 29. 0.1 hz to 10 hz rti voltage noise (g = 1000) current noise (fa/ hz) 10 100 1k frequency (hz) 10 1 100 1k 10k 03149-029 figure 30. current noise spectral density vs. frequency 1s/div 5pa/div 03149-030 figure 31. 0.1 hz to 10 hz current noise 0 5 10 15 20 25 30 output voltage (v p-p) frequency (hz) 1k 100k 10k 1m 03149-031 gain = 1 gain = 10, 100, 1000 v s = 15v figure 32. large signal frequency response 20s/div 0.002%/div 7.9s to 0.01% 8.5s to 0.001% 5v/div 03149-032 figure 33. large signal pulse response and settling time (g = 1), 0.002%/div
ad8221 rev. c | page 15 of 24 20s/div 4.9s to 0.01% 5.6s to 0.001% 5v/div 03149-033 0.002%/div figure 34. large signal pulse response and settling time (g = 10), 0.002%/div 20s/div 10.3s to 0.01% 13.4s to 0.001% 5v/div 03149-034 0.002%/div figure 35. large signal pulse response and settling time (g = 100), 0.002%/div 200s/div 83s to 0.01% 112s to 0.001% 5v/div 03149-035 0.002%/div figure 36. large signal pulse response and settling time (g = 1000), 0.002%/div 4s/div 20mv/div 03149-036 figure 37. small signal response, g = 1, r l = 2 k, c l = 100 pf 4s/div 20mv/div 03149-037 figure 38. small signal response, g = 10, r l = 2 k, c l = 100 pf 10s/div 20mv/div 03149-038 figure 39. small signal response, g = 100, r l = 2 k, c l = 100 pf
ad8221 rev. c | page 16 of 24 2 100s/div 20mv/div 03149-039 figure 40. small signal response, g = 1000, r l = 2 k, c l = 100 pf settling time (s) 0 10 5 15 output voltage step size (v) 5 0 10 15 20 03149-040 settled to 0.01% settled to 0.001% figure 41. settling time vs. step size (g = 1) settling time (s) 1 100 10 1000 gain 1 100 10 1000 03149-041 settled to 0.001% settled to 0.01% figure 42. settling time vs. gain for a 10 v step
ad8221 rev. c | page 17 of 24 theory of operation c1 c2 +v s +v s +in Cin Cv s Cv s 10k ? 10k ? 10k ? 400 ? 400 ? 10k ? ref output i b compensation i b compensation +v s Cv s +v s Cv s +v s v b i i r1 24.7k ? 24.7k ? r g q1 r2 q2 Cv s +v s Cv s a2 a1 a3 03149-042 figure 43. simplified schematic the ad8221 is a monolithic instrumentation amplifier b ased on the classic 3-op amp topology. input transistors q1 and q2 are biased at a fixed current so that any different ial input signal forces the output voltages of a1 and a2 to change acco rdingly. a signal applied to the input creates a current through r g , r1, and r2, such that the outputs of a1 and a2 deliver the correct voltage. topologically, q1, a1, r1 and q2, a2, r2 can be viewed as precision current feedback amplifiers. the amp lified differential and common-mode signals are applied to a difference amplifier that rejects the common-mode volt age but amplifies the differential voltage. the difference a mplifier employs innovations that result in low output offset vol tage as well as low output offset voltage drift. laser-trimmed re sistors allow for a highly accurate in-amp with gain error typ ically less than 20 ppm and cmrr that exceeds 90 db (g = 1). using superbeta input transistors and an i b compensation scheme, the ad8221 offers extremely high input impeda nce, low i b , low i b drift, low i os , low input bias current noise, and extremely low voltage noise of 8 nv/hz. the transfer function of the ad8221 is g r g k 4.49 1 users can easily and accurately set the gain using a sing le standard resistor. because the input amplifiers employ a current feedback architecture, the gain-bandwidth product of the ad822 1 increases with gain, resulting in a system that does not suff er from the expected bandwidth loss of voltage feedback architectures at higher gains. to maintain precision even at low input levels, special att ention was given to the design and layout of the ad8221, resultin g in an in-amp whose performance satisfies the most demandi ng applications. a unique pinout enables the ad8221 to meet a cmrr specification of 80 db at 10 khz (g = 1) and 110 db at 1 khz (g = 1000). the balanced pinout, shown in figure 44, redu ces the parasitics that had, in the past, adversely affected cmrr performance. in addition, the new pinout simplifies boa rd layout because associated traces are grouped together. f or example, the gain setting resistor pins are adjacent to th e inputs, and the reference pin is next to the output. 87 6 5 12 3 4 Cin r g r g +v s v out ref Cv s +in top view ad8221 03149-043 figure 44. pinout diagram
ad8221 rev. c | page 18 of 24 gain selection placing a resistor across the r g terminals set the gain of ad8221, which can be calculated by referring to table 6 or by using the gain equation. 1 k 4.49 g r g table 6. gains achieved using 1% resistors 1% standard table value of r g () calculated gain 49.9 k 1.990 12.4 k 4.984 5.49 k 9.998 2.61 k 19.93 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 the ad8221 defaults to g = 1 when no gain resistor is us ed. gain accuracy is determined by the absolute tolerance of r g . the tc of the external gain resistor increases the gain d rift of the instrumentation amplifier. gain error and gain drif t are kept to a minimum when the gain resistor is not used. layout careful board layout maximizes system performance. traces from the gain setting resistor to the r g pins should be kept as short as possible to minimize parasitic inductance. to ensu re the most accurate output, the trace from the ref pin should either be connected to the local ground of the ad82 21, as shown in figure 47, or connected to a voltage that is referen ced to the local ground of the ad8221. common-mode rejection one benefit of the high cmrr over frequency of the a d8221 is that it has greater immunity to disturbances, such as lin e noise and its associated harmonics, than do typical instrument ation amplifiers. typically, these amplifiers have cmrr fall-of f at 200 hz; common-mode filters are often used to compens ate for this shortcoming. the ad8221 is able to reject cmrr over a greater frequency range, reducing the need for filteri ng. a well implemented layout helps to maintain the high cmr r over frequency of the ad8221. input source impedance and capacitance should be closely matched. in addition, sour ce resistance and capacitance should be placed as close to t he inputs as permissible. grounding the output voltage of the ad8221 is developed with resp ect to the potential on the reference terminal. care should be taken to tie ref to the appropriate local ground. in mixed-signal environments, low level analog signals need to be isolated from the noisy digital environment. many ad cs have separate analog and digital ground pins. although it i s convenient to tie both grounds to a single ground plane, t he current traveling through the ground wires and pc boar d may cause hundreds of millivolts of error. therefore, separa te analog and digital ground returns should be used to minimize the current flow from sensitive points to the system ground. an example layout is shown in figure 45 and figure 46. 03149-044 figure 45. top layer of the ad8221-eval 03149-045 figure 46. bottom layer of the ad8221-eval
ad8221 rev. c | page 19 of 24 reference terminal as shown in figure 43, the reference terminal, ref, is at o ne end of a 10 k resistor. the output of the instrumentat ion amplifier is referenced to the voltage on the ref ter minal; this is useful when the output signal needs to be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level-shift the output so that the ad8221 can interface with an adc. the allowable reference voltage range is a function of the gain, input, and supply voltage. the ref pin should not exceed either +v s or Cv s by more than 0.5 v. for best performance, source impedance to the ref ter minal should be kept low, because parasitic resistance can adver sely affect cmrr and gain accuracy. power supply regulation and bypassing a stable dc voltage should be used to power the ins trumentation amplifier. noise on the supply pins can adversely affe ct performance. bypass capacitors should be used to decouple the amplifier. a 0.1 f capacitor should be placed close to each supply pin. as shown in figure 47, a 10 f tantalum capacitor can b e used further away from the part. in most cases, it can be sha red by other precision integrated circuits. ad8221 +v s +in Cin load ref 0.1f 10f 0.1f 10f Cv s v out 03149-046 figure 47. supply decoupling, ref, and output referred to local ground input bias current return path the input bias current of the ad8221 must have a retu rn path to common. when the source, such as a thermocouple, canno t provide a return current path, one should be created, a s shown in figure 48. +v s ref transformer thermocouple Cv s ad8221 +v s ref Cv s ad8221 capacitor coupled +v s ref c rr c Cv s ad8221 1 f high-pass = 2 ? rc 03149-047 figure 48. creating an i bias path input protection all terminals of the ad8221 are protected against esd, 1 k v human body model. in addition, the input structure allo ws for dc overload conditions below the negative supply, ?v s . the internal 400 ? resistors limit current in the event of a negative fault condition. however, in the case of a dc overload voltage above the positive supply, +v s , a large current flows directly through the esd diode to the positive rail. therefor e, an external resistor should be used in series with the input to limit current for voltages above +vs. in either scenario, the ad8221 c an safely handle a continuous 6 ma current, i = v in /r ext for positive overvoltage and i = v in /(400 ? + r ext ) for negative overvoltage. for applications where the ad8221 encounters extreme overload voltages, as in cardiac defibrillators, external se ries resistors, and low leakage diode clamps, such as bav199ls, fjh1100s, or sp720s should be used.
ad8221 rev. c | page 20 of 24 rf interference rf rectification is often a problem when amplifiers are used in applications where there are strong rf signals. the disturban ce can appear as a small dc offset voltage. high frequency si gnals can be filtered with a low-pass rc network placed at th e input of the instrumentation amplifier, as shown in figure 49. t he filter limits the input signal bandwidth according to the following relationship: ) 2(2 1 c d diff c c r filterfreq c cm rc filterfreq 2 1 where c d t 10 c c . r r ad8221 +15v +in Cin 0.1f 10f 10f 0.1f ref v out C15v r1 499 ? c d c c c c 10nf 1nf 1nf 03149-048 4.02k ? 4.02k ? figure 49. rfi suppression c d affects the difference signal, and c c affects the common- mode signal. values of r and c c should be chosen to minimize rfi. mismatch between the r c c at the positive input and the r c c at the negative input degrades the cmrr of the ad8 221. by using a value of c d one magnitude larger than c c , the effect of the mismatch is reduced, and therefore, performance is improved. precision strain gage the low offset and high cmrr over frequency of the a d8221 make it an excellent candidate for bridge measurements. as shown in figure 50, the bridge can be directly connecte d to the inputs of the amplifier. +5v +2.5v 03149-049 10f 0.1f ad8221 +in Cin r 350 ? 350 ? 350 ? 350 ? + C figure 50. precision strain gage conditioning 10 v signals for a +5 v differential input adc there is a need in many applications to condition 10 v signals. however, many of todays adcs and digital ics operate on much lower, single-supply voltages. furthermore, new adcs have differential inputs because they provide better common- mode rejection, noise immunity, and performance at low supply voltages. interfacing a 10 v, single-ended instrumentation amplifier to a +5 v, differential adc can be a challeng e. interfacing the instrumentation amplifier to the adc requires attenuation and a level shift. a solution is shown in figu re 51. +12v +in Cin 0.1f 10f 0.1f 10f C12v r3 1k ? +2.5v r4 1k ? ref r5 499 ? r2 10k ? r1 10k ? c1 470pf +12v 0.1f 0.1f C12v +12v +5v +5v 0.1f 10nf 0.1f C12v +12v 0.1f 0.1f C12v r6 27.4 ? r7 27.4 ? c2 220f 10f 0.1f 22f +5v 2.5v 220nf 10nf ad8221 ad8022 op27 ad8022 ad7723 vin(+) av dd agnd dgnd ref1 ref2 dv dd vin(C) ad780 gnd +v in v out 03149-050 (?) (?) figure 51. interfacing to a differential input adc
ad8221 rev. c | page 21 of 24 in this topology, an op27 sets the reference voltage of the ad8221. the output signal of the instrumentation amplifi er is taken across the out pin and the ref pin. two 1 k? resist ors and a 499 ? resistor attenuate the 10 v signal to +4 v . an optional capacitor, c1, can serve as an antialiasing filte r. an ad8022 is used to drive the adc. this topology has five benefits. in addition to level-shif ting and attenuation, very little noise is contributed to the syst em. noise from r1 and r2 is common to both of the inputs of the adc and is easily rejected. r5 adds a third of the dominant noise and therefore makes a negligible contribution to the noise of the system. the attenuator divides the noise from r3 an d r4. likewise, its noise contribution is negligible. the fourth benefit of this interface circuit is that the acquisition time of the ad8221 is reduced by a factor of 2. with the help of the op27, the ad8221 only needs to deliver one-half of the full swing; t herefore, signals can settle more quickly. lastly, the ad8022 settles quickl y, which is helpful because the shorter the settling time, t he more bits that can be resolved when the adc acquires data. this configuration provides attenuation, a level-shift, an d a convenient interface with a differential input adc w hile maintaining performance. ac-coupled instrumentation amplifier measuring small signals that are in the noise or offset of t he amplifier can be a challenge. figure 52 shows a circuit t hat can improve the resolution of small ac signals. the large gain reduces the referred input noise of the amplifier to 8 nv/hz. thus, smaller signals can be measured because the noise floor is lower. dc offsets that would have been gained by 100 are eliminated from the output of the ad8221 by the inte grator feedback network. at low frequencies, the op1177 forces the output of the ad8221 to 0 v. once a signal exceeds f high-pass , the ad8221 outputs the amplified input signal. ad8221 op1177 r 15.8k ? +v s +in Cin 0.1f 0.1f 0.1f 0.1f 10f 10f ref c 1f Cv s Cv s +v s +v s Cv s r 499 ? 1 ?5& f high-pass = 03149-051 figure 52. ac-coupled circuit
ad8221 rev. c | page 22 of 24 die information die size: 1575 m 2230 m die thickness: 381 m to minimize gain errors introduced by the bond wire s, use kelvin connections between the chip and the gain resistor, r g , by connecting pad 2a and pad 2b in parallel to one end of r g and pad 3a and pad 3b in parallel to the other end of r g . for unity gain applications where r g is not required, pad 2a and pad 2b must be bonded together as well as the pad 3a and pad 3b. 03149-104 1 2a 2b 3a 3b 4 5 6 8 7 logo figure 53. bond pad diagram table 7. bond pad information pad no. mnemonic pad coordinates 1 x (m) y (m) 1 ?in C379 +951 2a r g C446 +826 2b r g C615 +474 3a r g C619 +211 3b r g C490 C190 4 +in C621 C622 5 ?v s +635 C823 6 ref +649 C339 7 v out +612 +84 8 +v s +636 +570 1 the pad coordinates indicate the center of each pa d, referenced to the center of the die. the die ori entation is indicated by the logo, as shown in figu re 53.
ad8221 rev. c | page 23 of 24 outline dimensions compliant to jedec standa rds mo-187-aa 60 0.80 0.55 0.40 4 81 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0. 10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 54. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in des ign. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 80 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 55. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches)
ad8221 rev. c | page 24 of 24 ordering guide model 1 temperature range for specified performance operating 2 package description temperature range package option branding ad8221ar C40c to +85c C40c to +125c 8-lead soic_ n r-8 ad8221ar-reel C40c to +85c C40c to +125c 8- lead soic_n, 13" tape and reel r-8 ad8221ar-reel7 C40c to +85c C40c to +125c 8-lead soic_n, 7" tape and reel r-8 ad8221arz C40c to +85c C40c to +125c 8-lead soic _n r-8 ad8221arz-r7 C40c to +85c C40c to +125c 8-lead soic_n, 7" tape and reel r-8 ad8221arz-rl C40c to +85c C40c to +125c 8-lead soic_n, 13" tape and reel r-8 ad8221arm C40c to +85c C40c to +125c 8-lead msop rm-8 jla ad8221arm-reel C40c to +85c C40c to +125c 8-lead msop, 13" tape and reel rm-8 jla ad8221arm reel7 C40c to +85c C40c to +125c 8-le ad msop, 7" tape and reel rm-8 jla ad8221armz C40c to +85c C40c to +125c 8-lead mso p rm-8 jla# ad8221armz-r7 C40c to +85c C40c to +125c 8-lead msop, 7" tape and reel rm-8 jla# ad8221armz-rl C40c to +85c C40c to +125c 8-lead msop, 13" tape and reel rm-8 jla# ad8221br C40c to +85c C40c to +125c 8-lead soic_ n r-8 ad8221br-reel C40c to +85c C40c to +125c 8-lead soic_n, 13" tape and reel r-8 ad8221br-reel7 C40c to +85c C40c to +125c 8-lead soic_n, 7" tape and reel r-8 ad8221brz C40c to +85c C40c to +125c 8-lead soic_n r-8 ad8221brz-r7 C40c to +85c C40c to +125c 8-lead soic_n, 7" tap e and reel r-8 ad8221brz-rl C40c to +85c C40c to +125c 8-lead soic_n, 13" ta pe and reel r-8 ad8221ac-p7 C40c to +85c C40c to +125c die 1 z = rohs compliant part, # denotes rohs compliant product may be top or bottom marked. 2 see typical performance characteristics for expected operation from 85c to 125c. ?2003C2011 analog devices, inc. all rights reserved. tra demarks and registered trademarks are the property of their re spective owners. d03149C0C3/11(c)

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